Michel Rottleuthner: A Power Model of System Clocks

Current microcontroller units (MCUs) incorporate complex clock systems that span a huge configuration space. The potential of individual low-level clock configurations for minimizing energy has not come into focus, yet. In this talk, we present a generic power model of system clocks and a method to semi-empirically parametrize it per platform. Following a fully automated measurement and optimization process, we derive results for three platforms of largely diverse clock architectures. For all platforms, empirical evaluations show successful fits of the ground-truth power measurements. With the lean platform models at hand, we are able to (i) predict the power consumption for all configurations of the clock tree, which allows for (ii) static energy optimization at development time, and (iii) dynamic optimization of a Dynamic Voltage and Frequency Scaling (DVFS) service during runtime. The model also allows (iv)  to quantify the hidden energy consumption of internal clock nodes.